This invention relates in general to analog-to-digital (A/D) converters, and more particularly, to an A/D converter which varies both inputs of a comparator during a search by successive approximation to resolve the analog input signal into a multi-bit digital output signal.
A/D converters are well enough known in the art and many techniques have been developed for achieving the conversion from analog to digital format. One common A/D converter utilizes a large number of serially coupled resistors, 255 or more for 8-bit resolution, to generate an equal number of reference potentials each of which is compared to the analog input signal. A digital control signal systematically selects between the 255 reference potentials until the one closest in magnitude to the analog input signal is identified. The corresponding value of the 8-bit digital control signal provides the 8-bit digital output signal of the analog-to-digital conversion. One undesirable feature of the aforedescribed A/D converter is the requirement to generate 255 reference potentials and the need for 255 plus switches to sequential select therebetween. It is desirable to reduce the complexity of the A/D converter by limiting the number of reference potentials needed for the conversion.
In another known A/D converter, a subtraction technique is used to reduce the number of reference potentials wherein for each 8-bit A/D conversion, the analog input signal is sampled and applied to a first 4-bit A/D converter. A string of sixteen resistors is serially coupled between first and second power supply conductors, the latter of which are energized to positive and negative supply potentials representing the upper and lower acceptable limits of the analog input signal. The string of sixteen resistors provides a equal number of linearly graduated reference potentials which are systematically applied to the first A/D converter through respective switches for comparison to the sampled analog input signal. The first A/D converter generates the four most significant bits (MSB) corresponding to the highest reference potential that is still lower than the sampled analog input signal. The selected reference potential is then applied to the non-inverting input terminal of a unity gain operational amplifier, while the sampled analog input signal is applied the inverting input terminal thereby providing an output signal equal to the difference of the analog input signal and the selected reference potential. A second A/D converter is coupled to the output of the operational amplifier for resolving the difference signal into the four least significant bits (LSB). The combination of the four MSB and the four LSB is the 8-bit digital output signal representative of the magnitude of the analog input signal.
The previous A/D conversion technique suffers from a speed penalty because of the settling time of the operational amplifier. In addition, the offset voltage of the operational amplifier is typically amplified by a factor of two due to the interaction of the dynamic input signals which can cause an error of one LSB or more in the digital output signal. Hence, it is desirable to eliminate the need for the intermediate operational amplifier.
Hence, what is needed is an improved A/D converter using a search by successive approximation to reduce the number of reference potentials wherein a major portion of the analog input signal is first resolved into the most significant bits leaving a smaller portion thereof to be resolved into the least significant bits of the multi-bit digital output signal.